`timescale 1ns / 1ps 
/*
 Copyright 2020 Sean Xiao, jxzsxsp@qq.com
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 
 http://www.apache.org/licenses/LICENSE-2.0
 
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 */

module yue_riscv_cpu # (
    parameter [31:0] TMR_BASEADDR  = 32'h0200_0000,
    parameter [31:0] PLIC_BASEADDR = 32'h0c00_0000,
    parameter [31:0] ITCM_BASEADDR = 32'h8000_0000,
    parameter [31:0] DTCM_BASEADDR = 32'h9000_0000,
    parameter [31:0] UART_BASEADDR = 32'he000_0000,
    parameter [31:0] GPIO_BASEADDR = 32'hf000_0000

)
(
    input            sys_clk,
    
    input  [ 31: 0 ] i_GPIO_dina,
    output [ 31: 0 ] o_GPIO_douta,
    output [ 31: 0 ] o_GPIO_ta,
    
    input  [ 31: 0 ] i_GPIO_dinb,
    output [ 31: 0 ] o_GPIO_doutb,
    output [ 31: 0 ] o_GPIO_tb,
    
    input  [ 31: 0 ] i_GPIO_dinc,
    output [ 31: 0 ] o_GPIO_doutc,
    output [ 31: 0 ] o_GPIO_tc,

    input  [ 31: 0 ] i_GPIO_dind,
    output [ 31: 0 ] o_GPIO_doutd,
    output [ 31: 0 ] o_GPIO_td,

    output           txd_start,
    output [ 7:0 ]   txd_data,
    input            txd_done,
    
    input  [ 11:0 ]  code_addr,
    input  [ 31:0 ]  code_din,
    input            code_wea,
    
    input            l_clk,
    input            i_cpu_reset,
    input            rst_n
);


    
//================================ timer and its interrupt  processing =============
wire  [31:0] sft_int_v;
wire  [31:0] wr_timer_l;
wire  [31:0] wr_timer_h;
   
wire  [31:0] rd_timer_l;
wire  [31:0] rd_timer_h;
   
wire  [31:0] w_tcmp_l;
wire  [31:0] w_tcmp_h;
   
wire  [1:0]  timer_valid;
wire  [31:0] tm_ctrl;
//===================================================================================
wire  ext_irq_a;
wire  tmr_irq_a;
wire  sft_irq_a;
wire  dbg_irq_a;

wire  tmr_irq_r;
wire  ext_irq_r;
wire  sft_irq_r;
wire  dbg_irq_r;

wire  w_meie;
wire  w_msie;
wire  w_mtie;
wire  w_glb_irq;

yue_rv32i_core #
(
    .TMR_BASEADDR   ( TMR_BASEADDR ),
    .PLIC_BASEADDR  ( PLIC_BASEADDR ),
    .ITCM_BASEADDR  ( ITCM_BASEADDR ),
    .DTCM_BASEADDR  ( DTCM_BASEADDR ),
    .UART_BASEADDR  ( UART_BASEADDR ),
    .GPIO_BASEADDR  ( GPIO_BASEADDR )
)
yue_rv32i_core_inst
(
    .sys_clk        ( sys_clk ),
    
// ============================================    
    .i_GPIO_dina    ( i_GPIO_dina ),
    .o_GPIO_douta   ( o_GPIO_douta ),
    .o_GPIO_ta      ( o_GPIO_ta ),

    .i_GPIO_dinb    ( i_GPIO_dinb ),
    .o_GPIO_doutb   ( o_GPIO_doutb ),
    .o_GPIO_tb      ( o_GPIO_tb ),

    .i_GPIO_dinc    ( i_GPIO_dinc ),
    .o_GPIO_doutc   ( o_GPIO_doutc ),
    .o_GPIO_tc      ( o_GPIO_tc ),

    .i_GPIO_dind    ( i_GPIO_dind ),
    .o_GPIO_doutd   ( o_GPIO_doutd ),
    .o_GPIO_td      ( o_GPIO_td ),
// ============================================    
    .txd_start      ( txd_start ),
    .txd_data       ( txd_data ),
    .txd_done       ( txd_done ),
// ============================================    
    .o_sft_int_v    ( sft_int_v ),
    .o_timer_l      ( wr_timer_l ),
    .o_timer_h      ( wr_timer_h ),
             
    .i_timer_l      ( rd_timer_l ),
    .i_timer_h      ( rd_timer_h ), 
            
    .o_tcmp_l       ( w_tcmp_l ),
    .o_tcmp_h       ( w_tcmp_h ),
            
    .o_timer_valid  ( timer_valid ),
    .o_tm_ctrl      ( tm_ctrl ),
// ============================================    
    .code_addr      ( code_addr ),
    .code_din       ( code_din ),
    .code_wea       ( code_wea ),
// ============================================    
    .i_ext_irq      ( ext_irq_r ),
    .i_sft_irq      ( sft_irq_r ),
    .i_tmr_irq      ( tmr_irq_r ), 

    .o_meie         ( w_meie ),
    .o_msie         ( w_msie ),
    .o_mtie         ( w_mtie ),
    .o_glb_irq      ( w_glb_irq ),

// ============================================    
    .i_cpu_reset    ( i_cpu_reset ),
    .rst_n          ( rst_n )
);

yue_irq_clint yue_irq_clint_inst
(
    .sys_clk        ( sys_clk ),

    .i_sft_int_v    ( sft_int_v ),
    .i_timer_l      ( wr_timer_l ),
    .i_timer_h      ( wr_timer_h ),
               
    .o_timer_l      ( rd_timer_l ),
    .o_timer_h      ( rd_timer_h ),
               
    .i_tcmp_l       ( w_tcmp_l ),
    .i_tcmp_h       ( w_tcmp_h ),
               
    .i_timer_valid  ( timer_valid ),
    .i_tm_ctrl      ( tm_ctrl ),

    .clint_tmr_irq  ( tmr_irq_a ),
    .clint_sft_irq  ( sft_irq_a ),

    .l_clk          ( l_clk ),

    .rst_n          ( rst_n )
);


yue_irq_sync yue_irq_sync_inst
(
    .clk        ( sys_clk ),    

    .ext_irq_a  ( ext_irq_a & w_meie),
    .sft_irq_a  ( sft_irq_a & w_msie),
    .tmr_irq_a  ( tmr_irq_a & w_mtie),
    .dbg_irq_a  ( dbg_irq_a ),
/*
    .ext_irq_a  ( w_glb_irq & ext_irq_a & w_meie),
    .sft_irq_a  ( w_glb_irq & sft_irq_a & w_msie),
    .tmr_irq_a  ( w_glb_irq & tmr_irq_a & w_mtie),
    .dbg_irq_a  ( w_glb_irq & dbg_irq_a ),
*/
    .ext_irq_r  ( ext_irq_r ),
    .sft_irq_r  ( sft_irq_r ),
    .tmr_irq_r  ( tmr_irq_r ), 
    .dbg_irq_r  ( dbg_irq_r ),

    .rst_n      ( rst_n )
);


endmodule
